1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that includes a low-threshold-voltage MOSFET, and more particularly to a ring oscillator and a delay circuit.
2. Description of the Related Art
First, the DC operation of an inverter circuit will be described, with reference to FIG. 6 through FIG. 10.
For the purpose of this description, the power supply voltage (referred to as VCC hereinafter) will be made 3 V, and the threshold value of the MOSFET will be taken as the typical values in the past, this being a threshold value of 0.7 V at room temperature for an NMOS device (this threshold being hereinafter referred to as VTN) and a threshold value of -0.7 V at room temperature for an PMOS device (this threshold being hereinafter referred to as VTP).
First, let us consider the case in which the input voltage is VCC-.vertline.VTP.vertline. or greater. In this case, for a PMOS device, because the potential difference between the gate and the source is less than .vertline.VTP.vertline., the PMOS device is non-conducting, and for an NMOS device, because the potential difference between the gate and the source is greater than .vertline.VTN.vertline., the NMOS device conducts. Therefore, the output voltage is at the ground level.
Next, consider the case in which the input voltage is VCC-.vertline.VTP.vertline.-.vertline..alpha..vertline.. For a PMOS device, because the difference in potential between the gate and source is larger than .vertline.VTP.vertline. by the amount of .alpha., the PMOS device conducts, and for an NMOS device, because the potential difference between the gate and source is greater than .vertline.VTN.vertline., the NMOS device conducts. Note, however, because of (gm of the PMOS device)&lt;&lt;(gm of the NMOS device), the output voltage is near the ground level.
Next, consider the case in which the input voltage is GND+.vertline.VTN.vertline.+.vertline..alpha..vertline.. For a PMOS device, because the difference in potential between the gate and the source is greater than .vertline.VTP.vertline., the PMOS device conducts. For an NMOS device, because the difference in potential between the gate and source is greater than .vertline.VTN.vertline. by the amount .alpha., the NMOS device conducts. Note, however, because of (gm of the PMOS device)&gt;&gt;(gm of the NMOS device), the output voltage is near VCC.
Next, consider the case in which the input voltage is GND+.vertline.VTN.vertline.. In this case, for a PMOS device, because the difference in potential between the gate and source is greater than .vertline.VTP.vertline., the PMOS device conducts. For an NMOS device, because the difference in potential between the gate and source is lower than .vertline.VTN.vertline., the NMOS device is non-conducting. The output voltage, therefore, is VCC.
The foregoing description of the operation of an inverter assumes that the power supply voltage VCC is 3 V.
As is clear from the above-noted description of the operation of an inverter, to operate an inverter it is necessary that VCC be higher than .vertline.VTN.vertline.+.vertline.VTP.vertline.+.vertline..alpha..vertline .. For example, using the numerical example given above, this would be .vertline.1.4.vertline. V+.alpha..
Next, consider the case in which the power supply voltage is made low. FIG. 9 is a drawing that illustrates the operation at a VCC that is below the lower operating limit.
If the device is designed so that the MOSFET threshold voltage is a value that is lower than that described above, the VCC operating margin is broadened. However, there is the problem of a worsening of the current consumption characteristics when the semiconductor device is in the standby condition.
While the foregoing description was with regard to an inverter circuit, the characteristics of other logic gate circuits, such as NAND circuits and NOR circuits are approximately the same as an inverter circuit.
An oscillator circuit or delay circuit is used to provide a signal having an appropriate arbitrary time delay for another circuit within the semiconductor device. FIG. 11 shows an oscillator circuit of the past, and FIG. 12 shows a delay circuit of the past.
Next, the configuration and operation of the oscillator circuit of FIG. 11 will be described.
The NMOS transistors N5, N4, N11, N21 and N31 form a current mirror cicuit, and the PMOS transistors P4, P11, P21, and P31 form another current mirror cicuit. An inverter ring is formed by the transistors P11, P12, N12, N11, P21, P22, N22, N21, P31, P32, N32, and N31, as shown in FIG. 11.
The transistors P11, P21, P31, N11, N21, and N31, and the transistors P4 and N5 act as constant-current elements when operating, and act as current-blocking elements when in the standby condition. The activating signals of this circuit are TSTB and the compliment thereto, BSTB, and the output terminal of the circuit is OUT.
When operation of the circuit starts, a high level and a low level are applied to the activating signals TSTB and BSTB, respectively. A constant current is generated by the resistance R1 and the transistor N5 and, by means of a current mirror connection, this is reflected in the inverter ring. The inverter ring operates so as to oscillate within an operating current range that is limited by the above-described constant-current circuit. FIG. 13 shows the timing of this circuit, and FIG. 14 shows the dependence of the oscillation period TOSC on VCC.
The dependency on VCC of the oscillation period TOSC of the inverter ring that is controlled by the constant current is such that the oscillation period TOSC increases with an increase in VCC and decreases with a decrease in VCC.
Although the VCC dependency of the oscillation period TOSC is substantially linear, it is offset from the straight line in the region of VCCMIN, exhibiting a characteristic that approaches a fixed value as shown in FIG. 14.
Next, the delay circuit of FIG. 12 will be described.
This circuit is approximately the same as the oscillator circuit of FIG. 11. When operation starts, a low level and a high level are applied to the activation signals TSTB and BSTB, respectively. A constant current is generated by the resistance R1 and the transistor N5 and, by means of a current mirror connection, this is reflected in the inverter chain. The inverter chain operates so as to perform switching operation within an operating current range that is limited by the above-described constant-current circuit.
FIG. 15 is the timing diagram of the above-noted circuit, and FIG. 16 shows the dependency on VCC of the delay time TD of this circuit.
The VCC dependency of the delay time of the inverter chain that is controlled by a constant current is such that the delay time increases with an increase in VCC and decreases with a decrease of VCC. Although the VCC dependency of the delay time TD is substantially linear, it is offset from the straight line in the region of VCCMIN, exhibiting a characteristic that approaches a fixed value as shown in FIG. 16.
A problem that is associated with an oscillator circuit and delay circuit that have the above-described VCC dependency is the loss of circuit characteristics linearity. The oscillator circuit or delay circuit is used to provide a signal having an appropriate arbitrary time delay for another circuit within the semiconductor device. However, as noted above, at a VCC that is in the region of VCCMIN, it becomes impossible to provide a signal having an appropriate timing to another circuit, and because of this there is a rapid worsening of the overall semiconductor device characteristics at a VCC value in the region of VCCMIN.
The Japanese Unexamined Patent Publication (KOKAI) No. 4-346515 discloses BICMOS NAND circuit having low-threshold-voltage type MOSFETs, so as to reduce power consumption. However, this circuit is different from the present invention in terms of problem to be solved and constitution.